1. Field of the Invention
The present invention relates to a cascode circuit used mainly in a radiofrequency band of 800 MHz or higher.
2. Background Art
A cascode circuit in which two field effect transistors (hereinafter referred to as “FET”) having a Schottky junction gate are connected in cascode form is used in a radiofrequency amplifier circuit used in a radiofrequency band.
FIG. 11 is a circuit diagram showing a conventional cascode circuit. The cascode circuit has a first FET 1 having its source grounded, a second FET 2 having its source connected to the drain of the first FET 1, a capacitor 3 connected between the source of the first FET 1 and the gate of the second FET 2, a resistor 4 connected between the drain of the second FET 2 and the gate of the second FET 2, and a resistor 5 connected parallel to the capacitor 3 between the source of the first FET 1 and the gate of the second FET 2.
The capacitance C1 of the capacitor 3 and the resistance values R1 and R2 of the resistors 4 and 5 for determining the gate voltage of the second FET 2 are optimized to double the withstand voltage in comparison with an arrangement using a single FET and to obtain an output and a gain about twice as high as those in the case of the arrangement using a single FET (see, for example, Japanese Patent Laid-Open No. 2005-33650).
It is effective to adopt a microwave monolithic IC (MMIC) in which circuit elements including resistors, capacitors and matching lines are simultaneously fabricated, in reducing the cost and the circuit loss in a radiofrequency band of several GHz or higher. In conventional cascode circuits, therefore, a metal-insulator-metal (MIM) capacitor is used as capacitor 3.
FIG. 12 is a sectional view of a MIM structure, and FIG. 13 is a plan view of the MIM structure. An interwiring insulating film 7 of SiO2 or SiNx is formed between a piece of lower substratum wiring 6 and a piece of upper substratum wiring 8 formed over a semiconductor substrate 5. One end of the piece of upper substratum wiring 8 is grounded while one end of the piece of lower substratum wiring 6 is connected to the gate of the second FET 2.
Each resistor is formed as an implanted resistor or an epitaxial resistor by placing the active layer of the transistor in line form. FIG. 14 is a perspective view of an epitaxial resistor. A Schottky layer 12 is formed on a channel 11 and a high-concentration-doped semiconductor layer 13 high-concentration doped to be an n-type layer in ohmic contact is formed on the Schottky layer 12. The resistance value of the high-concentration-doped semiconductor layer 13 is determined the coping concentration of the doped layer. The sheet resistance of the concentration-doped semiconductor layer 13 is ordinarily low, about 100 Ω/□.
It is known that the optimum value of the capacitance value C1 of the capacitor 3 is as expressed by the following expression:
                              C          ⁢                                          ⁢          1                =                  Cgs                                                    1                2                            ⁢              gmRL                        -            1                                              (                  Formula          ⁢                                          ⁢          1                )            where Cgs is the gate-source capacitance, gm is the mutual conductance, and RL is an external load (fixed). Of these parameters, those varying due to variations in the active layer of the transistor are Cgs and gm. Cgs is determined generally by the depletion layer width during operation, while gm correlates with the sheet concentration Ns and pinch off voltage Vp of the active layer as well as the depletion layer width.
Causes of variations in transistor characteristics include variations in operating layer forming processes such as an implantation process and an epitaxial layer lamination process, and variations in device forming processes such as a gate forming process and a surface treatment process. In ordinary cases, the latter causes are dominant and the amounts of variation due to the latter causes are larger. In particular, when a gate is formed, Schottky characteristic parameters including the Schottky barrier potential difference Φb change easily depending on process conditions, because the Schottky junction is process-sensitive. The influence of the Schottky characteristic parameters on the transistor characteristics is considerably large.
Table 1 shows the results of simulation of gm and Cgs with respect to the value of Φb.
TABLE 1φbgmCgs0.75 eV0.36 S/mm12 pF0.55 eV0.36 S/mm10 pFThese parameters were computed by device simulation based on a low-noise high electron mobility transistor (HEMT) structure while the gate width Wg was set to 1 mm; the gate source voltage Vgs to −0.3 V; and the drain voltage Vd to 2 V. At the voltage Vgs=−0.3 V, gm is generally at its maximum. Vgs=−0.3 V and Vd=2 V are voltage regions ordinarily used in high-gain low-noise HEMTs.
From the simulation results shown above, it can be understood that when Φb is changed, only Cgs changes and the change in gm is substantially zero. From the results and Formula 1, the optimum capacitance value of C1 changes in correspondence with Cgs. However, the value of the MIM capacitor does not change in correspondence with Cgs. Therefore there is a problem that in a case where the optimum value of C1 varies due to variations in Cgs on a wafer plane, among wafers or among lots, the value of the MIM capacitor becomes different from the optimum value of C1.
Forming a piece of lower substratum wiring, interwiring insulating film and a piece of upper substratum wiring is required to form the MIM capacitor, and each of the processes of forming the wiring and film includes a transfer step. Therefore an increased number of masks are required and there is a possibility of the number of process steps being increased to several tens or more. In forming the MIM capacitor, there is a need to increase the thickness of interwiring insulating film to about several hundred nm in order to stabilize the capacitance value. If the thickness is increased, the interwiring distance is increased and the capacitance value per area is reduced. A need then arises to increase the pattern area. From this need, the chip area is increased and the number of chips per wafer is reduced, resulting in an increase in manufacturing cost.